CV

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Education

Ph.D in the Department of Electrical Engineering, City University of Hong Kong, 2025
B.Eng in the Department of Electrical Engineering, City University of Hong Kong, 2020

Work Experiences

Dec 2023 — May 2024: Research Intern in Huawei HK
- Research Intern - Huawei 2012 Laboratory, Theory Laboratory
- Participated in a cluster system development project, contuibute to the multithreading and distributed-system low-level operators optimization.
- Conducted several internal talks, technology sharings. And generated technical report.
July 2023 — Oct 2023: Research Intern in Zhijiang Lab, Hangzhou, China
- Research Intern - Zhijiang Lab
- Participated in a GPU-based high-performance computing system development project, contuibute to optimizing the low-level operators.
- Conducted several internal talks, technology sharings. And generated technical report.

Skills

C/C++ Development Tools: CLion, Git, Perf, Intel VTune Profilier.
Programming Languages: C/C++, MATLAB, Python.
Hardware Development Tools: Xilinx Vivado, Xilinx Vivado HLS, Verilator, VCS.
Hardware Description Languages: Verilog HDL, VHDL, Scala(Chisel, SpinalHDL).
Languages: Mandarin (Native), English (Proficient), Cantonese (Intermediate).

Research Experiences

June 2022 — Sept 2023: Design Space Exploration Framework on Optimised Polynomial Multiplication Architecture on FPGA
- Ph.D. Candidate - City University of Hong Kong, Hong Kong
- Proposing a novel NTT variant utilizing the radix-4 method, to reduce the computing complexity compared to traditional NTT method.
- Designing a highly efficient post-quantum crypto-system enhanced by the proposed split-radix NTT algorithm, showing significant performance improvements over the state-of-the-art designs on Xilinx Artix-7 FPGA.
- Developing a deep understanding of hardware systems and cryptography, and technical writing skills to produce high-quality research publications.
- Supervisor: Prof. Ray Cheung
July 2020 — June 2022: Optimised Post-Quantum Cryptographic System on FPGA
- Ph.D. Candidate - City University of Hong Kong, Hong Kong
- Proposing a novel NTT variant utilizing the split-radix method, to reduce the computing complexity compared to traditional NTT method.
- Designing a highly efficient post-quantum crypto-system enhanced by the proposed split-radix NTT algorithm, showing significant performance improvements over the state-of-the-art designs on Xilinx Artix-7 FPGA.
- Developing a deep understanding of hardware systems and cryptography, and technical writing skills to produce high-quality research publications.
- Supervisor: Prof. Ray Cheung
May 2020 — Feb 2022: Secure RISC-V Platform for IoT Devices
- Ph.D. Candidate - City University of Hong Kong, Hong Kong
- Conducting literature reviews and experimental analyses to evaluate the feasibility of implementing post-quantum cryptography, AES, and ECDSA on constrained devices with limited power and memory resources.
- Designing a hardware accelerator for the quantum-resistant cryptographic algorithm that can be extended to secure RISC-V IoT processors, leveraging knowledge of hardware design and cryptography.
- Collaborating with PI and other researchers on the project to design and implement the hardware accelerator and evaluating its effectiveness in secure IoT platforms.
- Supervisor: Prof. Ray Cheung
May 2019 — May 2020: Post-Quantum Cryptographic Hardware Design
- Final Year Project - City University of Hong Kong, Hong Kong
- Implemented a quantum-resistant cryptographic algorithm named as the Binary Ring LWE algorithm (BRLWE) in C, accelerated by an optimized NTT multiplication algorithm.
- Conducted a hardware/software co-design, resulting in an SoC platform called Brlwesoc with UART port and the BRLWE C program running on.
- Implemented the Brlwesoc on Lattice iCE40-HX8K FPGA board. Space, timing analysis and accuracy analysis are performed and the comparison on different parameter sets of the BRLWE is presented and discussed.
- Supervisor: Prof. Ray Cheung
May 2019 — Aug 2019: Hardware Security
- Research Assistant - LIRMM, Montpellier, France
- Conducting a feasibility study on implementing the PicoRV32 processor on FPGA for a lightweight SoC platform.
- Designing a hardware trojan in the PicoRV32 processor and attacked the AES program via simulation as part of the feasibility study on the lightweight SoC platform.
- Developing strong problem-solving skills, and experience with FPGA design and simulation tools.
- Working effectively both independently and as part of a team in a fast-paced and dynamic research environment.
- Supervisor: Dr. Sophie Dupuis

Publications

Algorithm-Hardware Co-Design of Split-Radix Discrete Galois Transformation for KyberKEM

G. Li, D. Chen, G. Mao, W. Dai, A. I. Sanka and R. C. C. Cheung, "Algorithm-Hardware Co-Design of Split-Radix Discrete Galois Transformation for KyberKEM," in IEEE Transactions on Emerging Topics in Computing, doi: 10.1109/TETC.2023.3270971.

High-performance and Configurable SW/HW Co-design of Post-quantum Signature CRYSTALS-Dilithium

Gaoyu Mao, Donglong Chen, Guangyan Li, Wangchen Dai, Abdurrashid Ibrahim Sanka, Çetin Kaya Koç, and Ray C. C. Cheung. 2023. High-performance and Configurable SW/HW Co-design of Post-quantum Signature CRYSTALS-Dilithium. ACM Trans. Reconfigurable Technol. Syst. 16, 3, Article 44 (September 2023), 28 pages. https://doi.org/10.1145/3569456

REALISE-IoT: RISC-V Based Efficient and Lightweight Public-key System for IoT Applications

Gaoyu Mao, Yao Liu, Wangchen Dai, Guangyan Li, Zhewen Zhang, Alan H. F. Lam, and Ray C. C. Cheung, "REALISE-IoT: RISC-V Based Efficient and Lightweight Public-Key System for IoT Applications," in IEEE Internet of Things Journal, doi: 10.1109/JIOT.2023.3296135.

ProgramGalois: A Programmable Generator of Radix-4 Discrete Galois Transformation Architecture for Lattice-based Cryptography

Guangyan Li, Zewen Ye, Donglong Chen, Wangchen Dai, Gaoyu Mao, Kejie Huang, and Ray C. C. Cheung. 2024. ProgramGalois: A Programmable Generator of Radix-4 Discrete Galois Transformation Architecture for Lattice-based Cryptography. ACM Trans. Reconfigurable Technol. Syst. Just Accepted (August 2024). https://doi.org/10.1145/3689437

Efficient Key-Switching for Word-Type FHE and GPU Acceleration

Jin, S., Gu, Z., Li, G., Chen, D., Koç, C. K., Cheung, R. C., & Dai, W. (2024). Efficient Key-Switching for Word-Type FHE and GPU Acceleration. Cryptology ePrint Archive.

PQNTRU: Acceleration of NTRU-based Schemes via Customized Post-Quantum Processor

Zewen Ye, Junhao Huang, Tianshun Huang, Yudan Bai, Jinze Li, Hao Zhang, Guangyan Li, Donglong Chen, Ray C. C. Cheung, and Kejie Huang. 2025. "PQNTRU: Acceleration of NTRU-based Schemes via Customized Post-Quantum Processor," in IEEE Transactions on Computers, doi: 10.1109/TC.2025.3540647.

High-Radix/Mixed-Radix NTT Multiplication Algorithm/Architecture Co-design over Fermat Modulus

Patents

Cryptosystem With Utilizing Split-Radix Discrete Galois Transformation (inventor) - U.S. Patent 2024/0430075 A1 - A method and system for key encapsulation processor with utilizing split-radix Discrete Galois Transformation for high performance.
A Processor For A Cryptosystem (inventor) - U.S. Patent 12,093,198 B2 - A method and system for digital signature service including hardware accelerator modules and software processor.

Selected Awards

CityU EE Graduate Research Seminar Awards - First Prize - Semester A 2022/23
2023 IC Design Invitational Competition for College Students from Across-the-Taiwan-Straits, Hong Kong and Macau (2023年海峡两岸暨港澳大学生集成电路与电子设计邀请赛) - First Prize - Sept 2023
Research Tuition Scholarship (RTS) - Full Tuition Fee - Academic Year 2023/24
2023 Guangdong Province Computer Society Outstanding paper award - 3rd Prize - - Jan 2024

LI Guangyan (Gavin)

CV